CEVA-X1641™
Product description The CEVA-X family of cores is based on CEVA's latest pioneering DSP architecture. This architecture offers best-in-class performance, scalability, and lowest cost-of-development for DSP deployment. CEVA-X1641 is a quad-MAC member of the CEVA-X DSP family consisting of 16-bit data width and four MAC units. CEVA-X1641 target markets include 4G (WiMAX, WiBro) cellular handsets and Software radio, smart phones / PDAs, Video & Audio processing for mobile devices, VoIP Gateways & broadband modems, and home entertainment (Digital TV, HDTV, PVR, HD-DVD). CEVA-X1641 is fully compatible to existing CEVA-X family members, the CEVA-X1620 and CEVA-X1622. High Performance at Low Power Consumption The CEVA-X1641 architecture has a unique mix of Very Long Instruction Word (VLIW) and Single Instruction Multiple Data (SIMD) architectures. The VLIW architecture allows a high level of concurrent instructions processing thus providing extended parallelism, as well as low power consumption		CEVA-X1641 Target Markets 4G and WiMAX cellular handsets and Software Radio SmartPhones / PDAs Video & Audio processing for mobile devices VoIP Gateways & broadband modems Home entertainment (Digital TV, HDTV, PVR, HD-DVD)
		CEVA-X1641 Product Note For a more in-depth look at the CEVA-X1641 DSP Core, Download the CEVA-X1641 Product Note ( pdf, 372kb)

SIMD architecture allows single instructions to operate on multiple data elements resulting in code size reduction and increased performance. Low power consumption is also achieved in the CEVA-X1641 by its instructions and dedicated mechanisms such as dynamic and selective units shutdowns and clock slow downs.

High-level Programming

CEVA-X1641 architecture is compiler-driven, implementing orthogonal instruction set and operands, load/store architecture, byte addressing and simple memory configuration (no X/Y partitioning).

CEVA-X1641 Block Diagram

The Computation and Bit Manipulation Unit is responsible for all DSP computations, and includes four independent functional units: Four 16x16-bit MAC units, 40-bit Shift unit and 40-bit Logical unit. The Data Address and Arithmetic Unit includes two identical Load/Store Units, responsible for generating all data memory accesses. The Scalar Unit is a 32-bit integer CPU block, supporting arithmetic, shift and bit manipulation operations on 32-bit data types. The Program Control Unit is responsible for the code flow, including sequential flow, branches, loops and interrupts. The Dispatch Unit analyses instruction packets and dispatches single instructions to the different functional units.

Technical Highlights High frequency – over 600 MHz @ 65nm G, worst case process and conditions Quad MAC 16-bit fixed point DSP Combination of VLIW and SIMD architecture concepts Up to 8 instructions issued simultaneously Variable instruction width (16/32-bit) and variable length of instruction packets Two level memory architecture Up to 4G byte addressable memory space 64K/96K/160K/288K-byte level 1 program TCM and cache 64K/128/256K-byte level 1 data TCM Program and data DMAs Nine stage pipeline All instructions can be conditionally executed

The data memory subsystem supports a user configurable size L1 memory and up to 4G byte of L2 memory, through an AHB-Lite system bus and a programmable DMA. The program memory subsystem supports a user configurable size of 64K/96K/160K/288K-byte level 1 program TCM and cache. Using a separate AHB-Lite system bus and a programmable DMA, these can be extended up to 4G byte in L2.

A separate IO space is used for peripherals and slow devices built around the DSP.

The CEVA-X1620 achieved the highest score for a licensable dual MAC DSP from BDTI (as measured by BDTIsimMark2000™), and the CEVA-X1641 is reaching even higher performance levels. To accomplish that, dedicated instructions and mechanisms were built into the architecture, supporting 1-cycle Viterbi butterfly (two ACS), 1.2-cycles FFT butterfly and various functions accelerating multimedia kernels.

Soft Core

CEVA-X1641 design implementations are Soft Core based, allowing the customer to select the optimal operating point in terms of die size, power consumption and performance. In addition, the customer has complete flexibility in selecting the foundry, process (e.g. 0.13µ, 90nm, 65nm) and complementary IPs.

CEVA-X1641 IP incorporates fully automated design flow supporting mainstream EDA tools, significantly shortens time-to-market. CEVA-X1641 design can be ported to an FPGA that can be used for product prototype, system integration, design acceleration and clarification.